FIG. 1 schematically illustrates a traditional general purpose I/O (GPIO) driver circuit. As shown, the circuit in FIG. 1 includes PMOS transistor 101 and NMOS transistor 103 coupled at their drains, which are further coupled to I/O pad 105 and ESD device 107. The source of PMOS transistor 101 is connected to power rail 109 (e.g., VDD) and the source of NMOS transistor 103 is connected to ground rail 111 (e.g., VSS). Under ESD zapping from PAD to VSS, ESD current may, for instance, travel through paths 113a (e.g., from I/O pad 105 to ground rail 111 through ESD device 107) and 113b (e.g., from I/O pad 105 to ground rail 111 through power clamp 115). Paths 113a and 113b are desired ESD bypass paths that are designed as bypass paths for ESD current. However, because control logic circuit 117 may leave the gate of NMOS transistor 103 coupled to a high state (e.g., gate node 119 may be floating) during an ESD event, the ESD current may also travel through undesired path 113c (e.g., from I/O pad 105 to ground rail 111 through NMOS transistor 103). Since NMOS transistor 103 is typically fully-silicided and much smaller in size than ESD device 107, NMOS transistor 103 will burn out much quicker from the ESD current. Thus, the ESD performance of GPIO drivers may be poor despite robust ESD protection devices included in the circuit (e.g., due to the drastic impact ESD current may have on driver transistors).
FIG. 2 schematically illustrates one solution to the floating gate issue in the circuit of FIG. 1 (e.g., gate node 119 being left floating). Like the circuit in FIG. 1, the circuit in FIG. 2 is a GPIO driver circuit that includes PMOS transistor 201 and NMOS transistor 203 coupled at their drains, which are further coupled to I/O pad 205 and ESD device 207. Moreover, power rail 209 is connected to the source of PMOS transistor 201 and ground rail 211 is connected to the source of NMOS transistor 203. The circuit in FIG. 2 also includes desired, designed paths 213a (e.g., from I/O pad 205 to ground rail 211 through ESD device 207) and 213b (e.g., from I/O pad 205 to ground rail 211 through power clamp 215) for ESD current during an ESD event. However, as shown, the ESD current will also flow through parasitic diode 217 (e.g., through path 213c) to activate level shift 219 that will, in turn, feed a ground potential to gate node 221 at the gate of NMOS transistor 203, turning off NMOS transistor 203 during the ESD event. Consequently, ESD current is prevented from flowing through and burning out NMOS transistor 203.
Nonetheless, typical level shifts (e.g., level shift 219) include complex control circuits for controlling the gate of driver transistors during an ESD event. Because these complex control circuits utilize a substantial portion of I/O area for each I/O cell (e.g., due to numerous additional transistors located in each I/O cell), I/O driver circuits with typical level shifts generally lack extra area for other important components (e.g., additional resistor/capacitor elements). In addition, typical level shifts may suffer “false triggering” during normal operation (e.g., due to the complexity of typical level shifts), negatively affecting the performance of the driver transistors during normal operation.
A need therefore exists for an ESD-robust I/O driver circuit with a more efficient and effective implementation for controlling the gates of driver transistors, and enabling methodology.